1. Field of the Invention
The present invention generally relates to a cluster tool and method of fabricating devices on semiconductor substrates. More specifically, the present invention relates to a cluster tool and method for process integration in manufacture of field effect transistors.
2. Description of the Related Art
Integrated circuits may include more than one million micro-electronic field effect transistors (e.g., complementary metal-oxide-semiconductor (CMOS) field effect transistors) that are formed on a substrate (e.g., semiconductor wafer) and cooperate to perform various functions within the circuit. A CMOS transistor comprises a gate structure disposed between source and drain regions that are formed in the substrate. The gate structure generally comprises a gate electrode and a gate dielectric. The gate electrode is disposed over the gate dielectric to control a flow of charge carriers in a channel region formed between the drain and source regions beneath the gate dielectric. To increase the speed of the transistor, the gate dielectric may be formed from a material having a dielectric constant greater than 4.0. Herein such dielectric materials are referred to as high-k materials.
Fabrication of gate structures of field effect transistors having the high-k gate dielectric comprises a series of processing steps (e.g., etching steps and the like) and control steps (e.g., measuring steps) which are performed using various substrate processing reactors and metrology tools. While maintaining vacuumed processing chambers, such reactors operate in atmospheric-pressure manufacturing regions of a semiconductor fab and are coupled together and with the metrology tools using atmospheric-pressure factory interfaces (i.e., transports for cassettes with the substrates).
In non-vacuumed environment, the substrates are exposed to mechanical and chemical contaminants, such as particles, traces of gaseous halogen-based reactants, and the like, that may damage the gate structures being fabricated. As gate structures become smaller and/or thinner to increase the device speed, the risk of contamination becomes increased. Additionally, the time spent on transferring the substrate between the processing reactors and between the processing reactors and metrology tools decreases productivity in manufacture of the field effect transistors.
Therefore, there is a need in the art for an improved cluster tool and method for process integration in manufacture of gate structures of field effect transistors.